Memory devices are typically provided as internal, semiconductor, integrated circuit devices in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.
Flash memory has developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Changes in threshold voltage (Vt) of the memory cells, through programming (which is often referred to as writing) of charge storage structures (e.g., floating gates or charge traps) or other physical phenomena (e.g., phase change or polarization), determine the data state (e.g., data value) of each memory cell. Common uses for flash memory and other non-volatile memory include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, mobile telephones, and removable memory modules, and the uses for non-volatile memory continue to expand.
A NAND flash memory is a common type of flash memory device, so called for the logical form in which the basic memory cell configuration is arranged. Typically, the array of memory cells for NAND flash memory is arranged such that the control gate of each memory cell of a row of the array is connected together to form an access line, such as a word line. Columns of the array include strings (often termed NAND strings) of memory cells connected together in series between a pair of select gates, e.g., a source select transistor and a drain select transistor. Each source select transistor may be connected to a source, while each drain select transistor may be connected to a data line, such as column bit line. Variations using more than one select gate between a string of memory cells and the source, and/or between the string of memory cells and the data line, are known.
Programming memory typically utilizes an iterative process of applying a programming pulse to a memory cell and verifying if that memory cell has reached its desired data state in response to that programming pulse, and repeating that iterative process until that memory cell passes the verification. Once a memory cell passes the verification, it may be inhibited from further programming, although other memory cells may still be enabled for programming for subsequent programming pulses. The iterative process can be repeated with changing (e.g., increasing) voltage levels of the programming pulse until each memory cell selected for the programming operation has reached its respective desired data state, or some failure is declared, e.g., reaching a maximum number of allowed programming pulses during the programming operation.
While programming a selected memory cell of one NAND string, a memory cell of an adjacent NAND string might be inhibited from programming. This typically involves boosting a voltage level of a channel region of the adjacent NAND string such that a programming voltage applied to its memory cell produces a voltage differential across its gate stack that is insufficient to appreciably change the threshold voltage of that memory cell. Where the boosting of the channel voltage is insufficient, unintended changes in the threshold voltage of the inhibited memory cell might occur. This is a condition known generally as program disturb.
To meet the demand for higher capacity memories, designers continue to strive for increasing memory density, i.e., the number of memory cells for a given area of an integrated circuit die. One way to increase memory density is to form NAND strings vertically along semiconductor pillars, which can act as channel regions of the NAND strings. However, such NAND string architecture may result in higher resistance levels for a channel region, thus making it more difficult to boost the voltage level of the channel region prior to applying a programming pulse.